1. Field of the Invention
The present invention relates to a method of manufacturing a MOS-type semiconductor device.
2. Description of the Related Art
FIG. 20 illustrates a cross-sectional view of a main portion including a surface MOS structure of a conventional power MOSFET which is one of general MOS-type semiconductor devices. A p-type well region 103 is formed on a surface layer of a semiconductor substrate (including an n+-type low-resistance semiconductor substrate 101 and an n−-type drift layer 102) of a MOSFET, and an n+-type source region 105 is formed thereon. The surface of the p-type well region 103 is sandwiched between the n+-type source region 105 and the surface of the n−-type drift layer 102. A gate electrode 107 formed of a polysilicon film or the like is stacked on the surface with a gate oxide film 106 interposed therebetween. Such a structure is referred to as a MOS gate structure or a surface MOS structure.
When a gate voltage equal to or higher than a threshold voltage is applied between the gate electrode 107 and a source electrode (not illustrated), an n-type inversion layer 103a in which electrons are accumulated is formed at the interface between the p-type well region 103 and the gate oxide film 106. The n-type inversion layer 103a becomes a passage for electrons connecting the source region and the n−-type drift layer 102 in the n-type region and is referred to as an n-channel. This n-channel provides a control function of turning the device on and off.
On the other hand, an active portion where a main current flows is formed in individual MOSFETs (device chips) arranged in a semiconductor wafer. In this active portion, a plurality of unit cells which uses the surface MOS structure as its unit cell is evenly distributed in the surface of the active portion and is arranged in parallel. In the individual MOSFET chip which is a device chip, the currents flowing through the respective unit cells are gathered in a metal electrode film that makes contact with the surfaces of a plurality of unit cells and output.
In a minimum unit cell that constitutes the surface MOS structure, the following parameters are known as factors that determine the characteristics of a MOS gate. Regarding the surface of the p-type well region 103, the length (the distance in the current flowing direction, also referred to as a channel length) of the channel forming region 103a and a surface impurity concentration thereof are the parameters. These parameters determine a gate threshold voltage with together with the thickness of the gate oxide film 106 provided on the surface of the channel forming region. The gate threshold voltage Vth is an important device design factor because this voltage directly influences the ON-resistance of a MOSFET. These parameters are determined carefully so that the parameters are maintained to be constant within the surface of the active portion with as little unevenness as possible. This is because the currents in unit cells are added in parallel to become a main current. That is, in order to allow the current to flow through the surface of the active portion of the MOSFET with as little unevenness as possible, it is preferable that all the currents in the respective unit cells flow with the same current density.
As thus explained, as a method of forming unit cells of the surface MOS structure as uniform as possible, a manufacturing method which employs self-alignment is known. This method eliminates a mask shift by forming a gate electrode formed of a polysilicon so that the end of the gate electrode is located at the end of an ion implantation region of the p-type well region 103 and the n+-type source region 105. An outline of a conventional manufacturing method (self-alignment method) will be described with reference to FIGS. 21 to 27 and FIG. 29. FIG. 29 is a schematic flowchart of the manufacturing process, and FIGS. 21 to 27 are cross-sectional views of a main portion including a surface MOS structure, illustrating the respective process steps.
A gate oxide film 106 is formed on an n−-type drift layer 102 formed of an n-type silicon semiconductor (step a1 of FIG. 29). Subsequently, a polysilicon film is formed on the gate oxide film 106, and etching is performed to obtain a necessary pattern, whereby a gate electrode 107 is formed (step a2).
Subsequently, boron ions are implanted using the gate electrode 107 as a mask (see FIG. 21), and an annealing process is performed to form a p-type well region 103 (see FIG. 22). Subsequently, a resist mask is formed on the gate electrode 107, and boron ions are implanted to form a p+-type contact region 104 (see FIG. 23). The resist mask is removed (see FIG. 24), a new resist mask 110 for forming an n+-type source region is formed, and arsenic ions are implanted (see FIG. 25) to form an n+-type source region 105 (see FIG. 26). Up to now, step a3 of FIG. 29 has been described.
When an interlayer insulating film 108 is formed so as to cover the gate electrode 107, a surface MOS structure is obtained (see FIG. 27). The p-type well region 103 and the n+-type source region 105 are formed by implanting ions using the same gate electrode 107 as a mask. Due to this, since a shift resulting from mask alignment is obviated, self-alignment is realized.
When the p-type well region 103 and the n+-type source region 105 are formed by the self-alignment method in this manner, since the channel length can be made uniform, the current flows uniformly through the surface of the active portion, and unevenness of the heating due to the current can be suppressed.
Moreover, Japanese Patent Application Publication No. H6-244428 discloses a method of forming a p-type well region and an n+-type source region using a thick oxide film as a mask rather than using a gate electrode, which also uses the self-alignment method. An outline of this method will be described with reference to FIGS. 28A to 28F which are cross-sectional views of a main portion including a surface MOS structure, illustrating the process steps.
An oxide film mask 111 is formed on an n−-type drift layer 102 formed of an n-type silicon semiconductor. Subsequently, boron ions are implanted using the oxide film mask 111 as a mask (see FIG. 28A), and an annealing process is performed to form a p-type well region 103 (see FIG. 28B). Subsequently, a resist mask is formed on the oxide film mask 111, and boron ions are implanted to form a p+-type contact region 104 (see FIG. 28C). The resist mask is removed (see FIG. 28D), a new resist mask 110 for forming an n+-type source region is formed, and arsenic ions are implanted (see FIG. 28E) to form an n+-type source region 105 (see FIG. 28F). After that, the oxide film mask 111 is removed completely (see FIG. 28G). Then, when a gate oxide film 106 and an interlayer insulating film 108 covering the gate electrode 107 are formed, the surface MOS structure is obtained (see FIG. 28H). The p-type well region 103 and the n+-type source region 105 are formed by implanting ions using the same oxide film mask 111 as a mask. Due to this, since a shift resulting from mask alignment is obviated, self-alignment is realized.
Japanese Patent Application Publication No. 2000-228520 discloses a technique of decreasing an impurity concentration of the channel forming region 103a in the p-type well region 103. According to this technique, first, a thick trench sidewall oxide film is formed on sidewalls of a trench as a post-treatment of trench sidewalls after trench etching, of a trench gate-type MOS transistor. Then, the oxide film is removed and a gate oxide film is formed. By doing so, the surface impurity concentration of a p-type base region (the same as the p-type well region) close to the trench sidewalls only can be decreased by taking advantage of impurities taken into the thick trench sidewall oxide film. Moreover, a threshold voltage can be decreased without decreasing withstanding power or the like of the device.
As described above, in the conventional method, the channel forming region 103a becomes the passage of a main current during the ON time, the channel forming region 103a is formed by the self-alignment method in order to maintain the resistance values of the channels distributed on the surface of the active portion of the MOSFET without any variation.
In general, a gate threshold voltage with of a MOSFET is determined by the thickness of the gate oxide film and a surface impurity concentration (hereinafter, an impurity concentration is sometimes referred to simply as a concentration) of the p-type well region 103. FIG. 17 is a diagram illustrating the relation between a gate oxide film and a gate threshold voltage Vth of a MOS-type semiconductor device having a general surface MOS structure. For example, if the surface impurity concentration of the p-type well region 103 is constant, the gate threshold voltage is determined by the gate oxide film thickness as illustrated in FIG. 17. The same is true for the gate oxide film. On the other hand, with regard to the gate threshold voltage Vth, the thickness of the gate oxide film and the surface impurity concentration of the p-type well region 103 have a trade-off relation.
On the other hand, a net doping concentration distribution of a region along line B1-B2 of a MOSFET illustrated in FIG. 20 shows such an oblique distribution that the concentration decreases gradually with a diffusion distance in the depth direction and a planar direction of the semiconductor substrate from the ion implantation region. In this case, the gate threshold voltage Vth is determined by the surface impurity concentration of the p-type well region 103 (the channel forming region 103a) near the junction terminal surface of the n+-type source region 105, in particular.
As described above, when the gate oxide film 106 is thick, by decreasing the surface impurity concentration near the n+-type source region 105 of the p-type well region 103 (the channel forming region 103a), it is possible to suppress an increase in the gate threshold voltage Vth.
However, when the surface impurity concentration of the p-type well region 103 is decreased, the entire concentration of the p-type well region 103 may also decrease. Thus, since the surface impurity concentration is closely related to other semiconductor characteristics such as a withstanding voltage or an ON-resistance of MOSFET, there is substantially no room for decreasing the surface impurity concentration. Therefore, it is difficult to decrease the thickness of the gate oxide film without increasing the gate threshold voltage, and there is a limit on decreasing the same.
Further, when the surface impurity concentration of the channel forming region 103a decreases, a depletion layer on the surface may extend too long, which make a short-channel effect occur easily and a parasitic bipolar transistor operate easily. Specifically, when the surface impurity concentration of the p-type well region 103 (the channel forming region 103a) is decreased in FIG. 20, it is possible to decrease the gate threshold voltage Vth. However, a low gate threshold voltage makes a parasitic transistor (a region indicated by reference numerals 105, 103, and 102) conductive easily, which makes it difficult to perform control with the gate. Further, in an OFF state, the depletion layer can easily spread in the channel forming region 103a, which may cause punch-through breakdown.